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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:06:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:06:45 -0700 |
| commit | 12c692f6eda7367527fde2a8aad49447a73aa643 (patch) | |
| tree | 8680eefff6897b2f4b33d12b5d96a6ea8c549b5b /tests/opt/opt_lut.ys | |
| parent | 78b30bbb1102047585d1a2eac89b1c7f5ca7344e (diff) | |
| download | yosys-12c692f6eda7367527fde2a8aad49447a73aa643.tar.gz yosys-12c692f6eda7367527fde2a8aad49447a73aa643.tar.bz2 yosys-12c692f6eda7367527fde2a8aad49447a73aa643.zip | |
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing
changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
Diffstat (limited to 'tests/opt/opt_lut.ys')
| -rw-r--r-- | tests/opt/opt_lut.ys | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index 59b12c351..a9fccbb62 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,4 +1,2 @@ read_verilog opt_lut.v -synth_ice40 -ice40_unlut -equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 +equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40 |