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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:26:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:26:55 -0700 |
| commit | d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5 (patch) | |
| tree | 46140158ab5a760da9280900e00240e5a1e6dca9 /tests/opt/opt_expr.ys | |
| parent | c7af71ecde65ad310e487a296b957678412fca74 (diff) | |
| parent | 509c353fe981c95ca667a637bf2b47477962a60b (diff) | |
| download | yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.tar.gz yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.tar.bz2 yosys-d672b1ddecf30cc7fd005ce7a06ab6c2d3dca1a5.zip | |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'tests/opt/opt_expr.ys')
| -rw-r--r-- | tests/opt/opt_expr.ys | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index f0306efa1..ecc2c8da8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -221,3 +221,73 @@ check equiv_opt opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y); + \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y)); +endmodule +EOT +check + +equiv_opt opt_expr +design -load postopt +select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y); + \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y)); +endmodule +EOT +check + +equiv_opt opt_expr +design -load postopt +select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y); + \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y)); +endmodule +EOT +check + +equiv_opt opt_expr +design -load postopt +select -assert-count 1 t:$shift r:A_WIDTH=3 %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y); + \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y)); +endmodule +EOT +check + +equiv_opt opt_expr +design -load postopt +select -assert-count 1 t:$shift r:A_WIDTH=10 %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y); + \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y)); +endmodule +EOT +check + +equiv_opt opt_expr -keepdc +design -load postopt +select -assert-count 1 t:$shift r:A_WIDTH=13 %i |