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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:26:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:31:08 -0700 |
| commit | aa4a69f89be9fcdcf20ca1c28d67444b994ec479 (patch) | |
| tree | 0bf10a7b71cc445296cd9e3c85c062af7869f8be /tests/opt/opt_clean_init.ys | |
| parent | fc9fb09a91220602538d99bfd08b1d8c34b69558 (diff) | |
| download | yosys-aa4a69f89be9fcdcf20ca1c28d67444b994ec479.tar.gz yosys-aa4a69f89be9fcdcf20ca1c28d67444b994ec479.tar.bz2 yosys-aa4a69f89be9fcdcf20ca1c28d67444b994ec479.zip | |
opt_clean: add init test
Diffstat (limited to 'tests/opt/opt_clean_init.ys')
| -rw-r--r-- | tests/opt/opt_clean_init.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys new file mode 100644 index 000000000..bfc383955 --- /dev/null +++ b/tests/opt/opt_clean_init.ys @@ -0,0 +1,13 @@ +logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1 +logger -expect-no-warnings +read_verilog <<EOT +module top; +(* init=1'b0 *) wire w = 1'b0; +(* init=1'bx *) wire x = 1'b0; +(* init=1'b1 *) wire y = 1'b0; +(* init=1'b0 *) wire z = 1'bx; +endmodule +EOT +clean +select -assert-count 1 a:init +select -assert-count 1 w:y a:init %i |