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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-13 00:43:15 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-14 01:06:23 +0200 |
commit | f7913285067ed30bf5087f265db7e0bd523af2b6 (patch) | |
tree | 520728e6d67c91e4597d39d3f04cd8d75d931156 /tests/memories | |
parent | 1f74ec3535dba67d3e71ab1b9bf509c86bdca560 (diff) | |
download | yosys-f7913285067ed30bf5087f265db7e0bd523af2b6.tar.gz yosys-f7913285067ed30bf5087f265db7e0bd523af2b6.tar.bz2 yosys-f7913285067ed30bf5087f265db7e0bd523af2b6.zip |
Add opt_mem_widen pass.
If all of us are wide, then none of us are!
Diffstat (limited to 'tests/memories')
-rw-r--r-- | tests/memories/wide_all.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/memories/wide_all.v b/tests/memories/wide_all.v new file mode 100644 index 000000000..f7bc3e5ce --- /dev/null +++ b/tests/memories/wide_all.v @@ -0,0 +1,36 @@ +// expect-wr-ports 2 +// expect-rd-ports 1 +// expect-wr-wide-continuation 2'10 + +module test( + input clk, + input [3:0] we, + input [6:0] ra, + input [5:0] wa, + input [31:0] wd, + output [15:0] rd +); + +reg [7:0] mem[3:254]; + +assign rd[7:0] = mem[{ra, 1'b0}]; +assign rd[15:0] = mem[{ra, 1'b1}]; + +initial begin + mem[5] = 8'h12; + mem[6] = 8'h34; + mem[7] = 8'h56; +end + +always @(posedge clk) begin + if (we[0]) + mem[{wa, 2'b00}] <= wd[7:0]; + if (we[1]) + mem[{wa, 2'b01}] <= wd[15:8]; + if (we[2]) + mem[{wa, 2'b10}] <= wd[23:16]; + if (we[3]) + mem[{wa, 2'b11}] <= wd[31:24]; +end + +endmodule |