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authorEddie Hung <eddie@fpgeh.com>2019-06-25 08:43:58 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-25 08:43:58 -0700
commitab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 (patch)
tree2f3ede3fb804ed9268ca759075551a09caf4fe96 /tests/memories
parentadd2d415fcab64eae8819021ad1b8dd1b56e6bf2 (diff)
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Add testcase from #335, fixed by #1130
Diffstat (limited to 'tests/memories')
-rw-r--r--tests/memories/issue00335.v28
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v
new file mode 100644
index 000000000..f3b6e5dfe
--- /dev/null
+++ b/tests/memories/issue00335.v
@@ -0,0 +1,28 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module ram2 (input clk,
+ input sel,
+ input we,
+ input [SIZE-1:0] adr,
+ input [63:0] dat_i,
+ output reg [63:0] dat_o);
+ parameter SIZE = 5; // Address size
+
+ reg [63:0] mem [0:(1 << SIZE)-1];
+ integer i;
+
+ initial begin
+ for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
+ mem[i] <= 0;
+ end
+
+ always @(posedge clk)
+ if (sel) begin
+ if (~we)
+ dat_o <= mem[adr];
+ else
+ mem[adr] <= dat_i;
+ end
+endmodule