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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 17:10:47 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 17:10:47 -0700 |
| commit | 2dffa4685b830313204f5d04314a14ed6ecac8ec (patch) | |
| tree | 023b8e9760f344f59f26efbe3912c3f610ff8bfe /tests/memories | |
| parent | d26646051c4ae9740decd5d76eec6a3afd63844a (diff) | |
| download | yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.tar.gz yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.tar.bz2 yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.zip | |
Add "-W' wire delay arg to abc9, use from synth_xilinx
Diffstat (limited to 'tests/memories')
0 files changed, 0 insertions, 0 deletions