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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-10 19:42:10 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-13 23:08:32 +0200 |
commit | 9fdedf4d1c5b1715f98ad107d322966eaee91f20 (patch) | |
tree | c2eae3346017601798c4931395600928646816fe /tests/memories/trans_sdp.v | |
parent | 616ace2d9299eee2006650ed3f13e9241664ad20 (diff) | |
download | yosys-9fdedf4d1c5b1715f98ad107d322966eaee91f20.tar.gz yosys-9fdedf4d1c5b1715f98ad107d322966eaee91f20.tar.bz2 yosys-9fdedf4d1c5b1715f98ad107d322966eaee91f20.zip |
memory_dff: Recognize soft transparency logic.
Diffstat (limited to 'tests/memories/trans_sdp.v')
-rw-r--r-- | tests/memories/trans_sdp.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/memories/trans_sdp.v b/tests/memories/trans_sdp.v new file mode 100644 index 000000000..b89f2ccf0 --- /dev/null +++ b/tests/memories/trans_sdp.v @@ -0,0 +1,21 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk +// expect-rd-en \re + +module top(input clk, we, re, input [7:0] ra, wa, wd, output reg [7:0] rd); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (we) + mem[wa] <= wd; + + if (re) begin + rd <= mem[ra]; + if (we && ra == wa) + rd <= wd; + end +end + +endmodule |