diff options
author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-05-27 21:08:11 +0200 |
---|---|---|
committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-08-11 14:17:48 +0200 |
commit | 72d86c327e203a097f15e502e6a90f1e6d345d7e (patch) | |
tree | 2387fd14ea61f265e900f46fca70b78e842c574b /tests/memories/read_two_mux.v | |
parent | 24027b5446ffa9d47e00e2ab8bc773fdebc246bd (diff) | |
download | yosys-72d86c327e203a097f15e502e6a90f1e6d345d7e.tar.gz yosys-72d86c327e203a097f15e502e6a90f1e6d345d7e.tar.bz2 yosys-72d86c327e203a097f15e502e6a90f1e6d345d7e.zip |
memory_dff: Recognize read ports with reset / initial value.
Diffstat (limited to 'tests/memories/read_two_mux.v')
-rw-r--r-- | tests/memories/read_two_mux.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v index 4f2e7e1cd..8b609c552 100644 --- a/tests/memories/read_two_mux.v +++ b/tests/memories/read_two_mux.v @@ -1,6 +1,9 @@ // expect-wr-ports 1 // expect-rd-ports 1 -// expect-no-rd-clk +// expect-rd-clk \clk +// expect-rd-en \re +// expect-rd-srst-sig \reset +// expect-rd-srst-val 8'00000000 module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata); |