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authorKrystalDelusion <krystinedawn@yosyshq.com>2022-07-07 11:10:33 +1200
committerKrystalDelusion <krystinedawn@yosyshq.com>2023-02-21 05:23:15 +1300
commit7f033d3c1f4604d303da237fbc7a38ee503416ad (patch)
treeab936013736da16465f74fe771dd08f5fbf261d6 /tests/memlib/memlib_lut.txt
parentaf1b9c9e070dd5873871c73c5762fbefd345a8c9 (diff)
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More tests in memlib/generate.py
Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
Diffstat (limited to 'tests/memlib/memlib_lut.txt')
-rw-r--r--tests/memlib/memlib_lut.txt18
1 files changed, 17 insertions, 1 deletions
diff --git a/tests/memlib/memlib_lut.txt b/tests/memlib/memlib_lut.txt
index 0cc8fda15..9f6d84123 100644
--- a/tests/memlib/memlib_lut.txt
+++ b/tests/memlib/memlib_lut.txt
@@ -1,7 +1,23 @@
ram distributed \RAM_LUT {
abits 4;
width 4;
- init any;
+ ifdef INIT_NONE {
+ option "INIT" "NONE" {
+ init none;
+ }
+ } else ifdef INIT_ZERO {
+ option "INIT" "ZERO" {
+ init zero;
+ }
+ } else ifdef INIT_NO_UNDEF {
+ option "INIT" "NO_UNDEF" {
+ init no_undef;
+ }
+ } else {
+ option "INIT" "ANY" {
+ init any;
+ }
+ }
cost 4;
port ar "R" {
}