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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-06 16:30:56 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 982a11c709b4b363f85ae52a127f8a98bda30a3f (patch) | |
| tree | de2dd78747314064b3a7731fc4791b0ec7bfb77d /tests/memlib/memlib_block_sdp_1clk.txt | |
| parent | 2a2dc12eb69f2e904609e5b8275ec885e21ecd26 (diff) | |
| download | yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.gz yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.bz2 yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.zip | |
Add memory_libmap tests.
Diffstat (limited to 'tests/memlib/memlib_block_sdp_1clk.txt')
| -rw-r--r-- | tests/memlib/memlib_block_sdp_1clk.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/memlib/memlib_block_sdp_1clk.txt b/tests/memlib/memlib_block_sdp_1clk.txt new file mode 100644 index 000000000..07c76c2a2 --- /dev/null +++ b/tests/memlib/memlib_block_sdp_1clk.txt @@ -0,0 +1,22 @@ +ram block \RAM_BLOCK_SDP_1CLK { + cost 64; + abits 10; + widths 1 2 4 8 16 per_port; + init any; + port sw "W" { + clock anyedge "C"; + ifdef TRANS_OLD { + option "TRANS" 0 { + wrtrans "R" old; + } + } + ifdef TRANS_NEW { + option "TRANS" 1 { + wrtrans "R" new; + } + } + } + port sr "R" { + clock anyedge "C"; + } +} |