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| author | whitequark <whitequark@whitequark.org> | 2020-04-24 18:35:53 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-24 18:35:53 +0000 |
| commit | a0e658d412269d0477ce6982cb0f3c7a0dba38f6 (patch) | |
| tree | 7e2b14a6d221d50ba81d8b4c7c2579f8baba375b /tests/lut | |
| parent | f88378ae616b331d43ccc99797e239785bab7644 (diff) | |
| download | yosys-a0e658d412269d0477ce6982cb0f3c7a0dba38f6.tar.gz yosys-a0e658d412269d0477ce6982cb0f3c7a0dba38f6.tar.bz2 yosys-a0e658d412269d0477ce6982cb0f3c7a0dba38f6.zip | |
cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.`
The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
Diffstat (limited to 'tests/lut')
0 files changed, 0 insertions, 0 deletions