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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 16:43:24 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-25 16:43:24 -0700 |
| commit | a009314597b2d71cb786745c516e53dff4b21a00 (patch) | |
| tree | cfe277ffa619e7857f3ddded14f25149c806ba0d /tests/ice40 | |
| parent | 739c6213303da2463949a229c9c62db40eaa9cc5 (diff) | |
| parent | b66364ada279c1fb81583003001b332dd4521f93 (diff) | |
| download | yosys-a009314597b2d71cb786745c516e53dff4b21a00.tar.gz yosys-a009314597b2d71cb786745c516e53dff4b21a00.tar.bz2 yosys-a009314597b2d71cb786745c516e53dff4b21a00.zip | |
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
ICE40 tests. adffs test update (equiv_opt -multiclock).
Diffstat (limited to 'tests/ice40')
| -rw-r--r-- | tests/ice40/adffs.v | 20 | ||||
| -rw-r--r-- | tests/ice40/adffs.ys | 13 |
2 files changed, 14 insertions, 19 deletions
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 93c8bf52c..09dc36001 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -22,29 +22,25 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk, posedge pre ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) + always @( negedge clk, negedge pre ) + if ( !pre ) q <= 1'b1; else q <= d; @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index 14b251c5c..548060b66 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,11 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFN -select -assert-count 2 t:SB_DFFSR -select -assert-count 7 t:SB_LUT4 -select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D +select -assert-count 1 t:SB_DFFNS +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D |