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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 12:38:28 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 12:38:28 +0300 |
| commit | 86f1375ecd3e6721a0e5da469672db890926914e (patch) | |
| tree | 1139af0b527695d94bb69e1aad50a64f0ef96a3e /tests/ice40 | |
| parent | f23b540b45fb485e38cb0a86e67cddb11dbd2a20 (diff) | |
| download | yosys-86f1375ecd3e6721a0e5da469672db890926914e.tar.gz yosys-86f1375ecd3e6721a0e5da469672db890926914e.tar.bz2 yosys-86f1375ecd3e6721a0e5da469672db890926914e.zip | |
Fix test for counter
Diffstat (limited to 'tests/ice40')
| -rw-r--r-- | tests/ice40/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys index fb32e67a5..c65c21622 100644 --- a/tests/ice40/counter.ys +++ b/tests/ice40/counter.ys @@ -5,7 +5,7 @@ flatten equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 7 t:SB_CARRY +select -assert-count 6 t:SB_CARRY select -assert-count 8 t:SB_DFFR select -assert-count 8 t:SB_LUT4 select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D |