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authorEddie Hung <eddie@fpgeh.com>2019-08-30 12:22:59 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-30 12:22:59 -0700
commit76a52712dac4f28fbc3c5611911310d252cd91a6 (patch)
tree2cdb5b7820be012148ef7b32e6869ba0aec5628b /tests/ice40
parentc1459bc748d0d2c47dcb2366e5a0893736d6d463 (diff)
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Improve tests/ice40/macc.ys for SB_MAC16
Diffstat (limited to 'tests/ice40')
-rw-r--r--tests/ice40/macc.v4
-rw-r--r--tests/ice40/macc.ys13
2 files changed, 10 insertions, 7 deletions
diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
index 63a3d3a74..6c3676c83 100644
--- a/tests/ice40/macc.v
+++ b/tests/ice40/macc.v
@@ -2,8 +2,8 @@
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
*/
module top(clk,a,b,c,set);
-parameter A_WIDTH = 4;
-parameter B_WIDTH = 3;
+parameter A_WIDTH = 6 /*4*/;
+parameter B_WIDTH = 6 /*3*/;
input set;
input clk;
input signed [(A_WIDTH - 1):0] a;
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
index fe5b5f662..0f4c19be5 100644
--- a/tests/ice40/macc.ys
+++ b/tests/ice40/macc.ys
@@ -1,10 +1,13 @@
read_verilog macc.v
proc
hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
+async2sync
+equiv_opt -run prove: -assert null
+
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 38 t:SB_LUT4
-select -assert-count 3 t:SB_CARRY
-select -assert-count 7 t:SB_DFFSR
-select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D
+select -assert-count 1 t:SB_MAC16
+select -assert-none t:SB_MAC16 %% t:* %D