diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 15:50:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:05:12 -0700 |
| commit | 698a0e3aafcae48535c68996fccf002c0e0e3aea (patch) | |
| tree | 66529d401e0ab1c80828813a68638ad5bcdabbb4 /tests/ice40 | |
| parent | 43e7c4917ad42b01d34b496c35798416a050aa61 (diff) | |
| download | yosys-698a0e3aafcae48535c68996fccf002c0e0e3aea.tar.gz yosys-698a0e3aafcae48535c68996fccf002c0e0e3aea.tar.bz2 yosys-698a0e3aafcae48535c68996fccf002c0e0e3aea.zip | |
WIP for equivalency checking memories
Diffstat (limited to 'tests/ice40')
| -rw-r--r-- | tests/ice40/memory.ys | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index fa5d004b0..9b7490cd8 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,5 +1,17 @@ read_verilog memory.v -synth_ice40 +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D |