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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 12:36:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:05:12 -0700 |
| commit | 61087329efcfac45de6b69ded33f38c8f8817eef (patch) | |
| tree | ac1960ecfc1eef5989d2821a6e817d847becdf7f /tests/ice40 | |
| parent | f9906eed68beab359ed83beee2bcf42ffac908c3 (diff) | |
| download | yosys-61087329efcfac45de6b69ded33f38c8f8817eef.tar.gz yosys-61087329efcfac45de6b69ded33f38c8f8817eef.tar.bz2 yosys-61087329efcfac45de6b69ded33f38c8f8817eef.zip | |
Fix tribuf test
Diffstat (limited to 'tests/ice40')
| -rw-r--r-- | tests/ice40/tribuf.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index ef4266959..d1e1b3108 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -2,7 +2,7 @@ read_verilog tribuf.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ |