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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-21 21:52:07 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-21 21:52:07 +0300 |
commit | d945b8a357c567f5f3565983da09f24c0f295461 (patch) | |
tree | e5b74e096ae940628d547acbf0cb139519918f24 /tests/ice40/mux.ys | |
parent | b835ec37cbb56bc3b55fe53eb85375ad5ac98f27 (diff) | |
download | yosys-d945b8a357c567f5f3565983da09f24c0f295461.tar.gz yosys-d945b8a357c567f5f3565983da09f24c0f295461.tar.bz2 yosys-d945b8a357c567f5f3565983da09f24c0f295461.zip |
Fix all comments from PR
Diffstat (limited to 'tests/ice40/mux.ys')
-rw-r--r-- | tests/ice40/mux.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 3da9ef433..9e3d87b7f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,4 +1,4 @@ - +read_verilog mux.v synth_ice40 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt |