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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:34:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:46:53 -0700 |
| commit | dd42aa87b9b3bb041cbfe49079c6538f0a6d5646 (patch) | |
| tree | 225509531df1226c543c5493c4d92f8dcc23b287 /tests/ice40/ice40_opt.ys | |
| parent | d46d38e4d5e1502ea5cb6075161c87bd837af9eb (diff) | |
| download | yosys-dd42aa87b9b3bb041cbfe49079c6538f0a6d5646.tar.gz yosys-dd42aa87b9b3bb041cbfe49079c6538f0a6d5646.tar.bz2 yosys-dd42aa87b9b3bb041cbfe49079c6538f0a6d5646.zip | |
Add ice40_opt test
Diffstat (limited to 'tests/ice40/ice40_opt.ys')
| -rw-r--r-- | tests/ice40/ice40_opt.ys | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys new file mode 100644 index 000000000..18e0d2b8a --- /dev/null +++ b/tests/ice40/ice40_opt.ys @@ -0,0 +1,24 @@ +read_verilog -icells -formal <<EOT +module top(input CI, I0, output CO, O); + wire A = 1'b0, B = 1'b0; + \$__ICE40_CARRY_WRAPPER #( + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(~16'b 0110_1001_1001_0110) + ) fadd ( + .A(A), + .B(B), + .CI(CI), + .I0(I0), + .I3(CI), + .CO(CO), + .O(O) + ); +endmodule +EOT + +equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt +design -load postopt +select -assert-count 1 t:$lut |