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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 13:22:11 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 13:22:11 +0300 |
| commit | f4a48ce8e6785fe9828b8896b9a60a74580dc2eb (patch) | |
| tree | a1fc9c17cfdbf5186381881ddeb9c418d2263b7a /tests/ice40/div_mod.ys | |
| parent | 86f1375ecd3e6721a0e5da469672db890926914e (diff) | |
| download | yosys-f4a48ce8e6785fe9828b8896b9a60a74580dc2eb.tar.gz yosys-f4a48ce8e6785fe9828b8896b9a60a74580dc2eb.tar.bz2 yosys-f4a48ce8e6785fe9828b8896b9a60a74580dc2eb.zip | |
fix div_mod test
Diffstat (limited to 'tests/ice40/div_mod.ys')
| -rw-r--r-- | tests/ice40/div_mod.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 96753b4ef..f55490572 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -4,6 +4,6 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 88 t:SB_LUT4 +select -assert-count 62 t:SB_LUT4 select -assert-count 65 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D |