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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 15:52:25 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 15:52:25 +0300 |
| commit | 71dd412ac55860cbf51d91d26088515978f70116 (patch) | |
| tree | c13ac7fde357fd1a4c0ff485a3c66bcdc40bfdca /tests/ice40/div_mod.ys | |
| parent | 153ec0541c17ee8fad093c002a2724bc33dfe4b9 (diff) | |
| download | yosys-71dd412ac55860cbf51d91d26088515978f70116.tar.gz yosys-71dd412ac55860cbf51d91d26088515978f70116.tar.bz2 yosys-71dd412ac55860cbf51d91d26088515978f70116.zip | |
Fix tests; Remove simulation;
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
Diffstat (limited to 'tests/ice40/div_mod.ys')
| -rw-r--r-- | tests/ice40/div_mod.ys | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 28f31136b..f66cb99dd 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,5 +1,6 @@ synth_ice40 -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 -select -assert-count 89 t:SB_LUT4 -select -assert-count 66 t:SB_CARRY -write_verilog ./temp/div_mod_synth.v +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt +select -assert-count 85 t:SB_LUT4 +select -assert-count 54 t:SB_CARRY |