diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 12:35:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:05:12 -0700 |
| commit | f9906eed68beab359ed83beee2bcf42ffac908c3 (patch) | |
| tree | cfc5831a72d320f861ddb742833959918191da7c /tests/ice40/dffs.ys | |
| parent | 9224b3bc1721ae45abf11594b3ab9a58e50aa86f (diff) | |
| download | yosys-f9906eed68beab359ed83beee2bcf42ffac908c3.tar.gz yosys-f9906eed68beab359ed83beee2bcf42ffac908c3.tar.bz2 yosys-f9906eed68beab359ed83beee2bcf42ffac908c3.zip | |
Fix comments
Diffstat (limited to 'tests/ice40/dffs.ys')
| -rw-r--r-- | tests/ice40/dffs.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index b14346f5a..ee7f884b1 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -2,7 +2,7 @@ read_verilog dffs.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF |