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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-21 21:52:07 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-21 21:52:07 +0300 |
| commit | d945b8a357c567f5f3565983da09f24c0f295461 (patch) | |
| tree | e5b74e096ae940628d547acbf0cb139519918f24 /tests/ice40/add_sub.ys | |
| parent | b835ec37cbb56bc3b55fe53eb85375ad5ac98f27 (diff) | |
| download | yosys-d945b8a357c567f5f3565983da09f24c0f295461.tar.gz yosys-d945b8a357c567f5f3565983da09f24c0f295461.tar.bz2 yosys-d945b8a357c567f5f3565983da09f24c0f295461.zip | |
Fix all comments from PR
Diffstat (limited to 'tests/ice40/add_sub.ys')
| -rw-r--r-- | tests/ice40/add_sub.ys | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index c2ee3a843..84f31ec53 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,7 +1,10 @@ -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 12 t:SB_LUT4 -select -assert-count 7 t:SB_CARRY -select -assert-count 2 t:$logic_and -select -assert-count 2 t:$logic_or +read_verilog add_sub.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + |