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author | Clifford Wolf <clifford@clifford.at> | 2014-08-01 03:57:37 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-01 03:57:37 +0200 |
commit | 5e641acc905a5c99d037378f6b7a481c43eb7de0 (patch) | |
tree | 9b2ab0d52d0e6469ee42132872f88f6d524f08c2 /tests/hana/test_simulation_sop.v | |
parent | 03ef9a75c64f79596d6c931a1401184c33f9346b (diff) | |
download | yosys-5e641acc905a5c99d037378f6b7a481c43eb7de0.tar.gz yosys-5e641acc905a5c99d037378f6b7a481c43eb7de0.tar.bz2 yosys-5e641acc905a5c99d037378f6b7a481c43eb7de0.zip |
Consolidated hana test benches into fewer files
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
Diffstat (limited to 'tests/hana/test_simulation_sop.v')
-rw-r--r-- | tests/hana/test_simulation_sop.v | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/tests/hana/test_simulation_sop.v b/tests/hana/test_simulation_sop.v new file mode 100644 index 000000000..79870cf0c --- /dev/null +++ b/tests/hana/test_simulation_sop.v @@ -0,0 +1,65 @@ + +// test_simulation_sop_basic_10_test.v +module f1_test(input [1:0] in, input select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + endcase +endmodule + +// test_simulation_sop_basic_11_test.v +module f2_test(input [3:0] in, input [1:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + endcase +endmodule + +// test_simulation_sop_basic_12_test.v +module f3_test(input [7:0] in, input [2:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + endcase +endmodule + +// test_simulation_sop_basic_18_test.v +module f4_test(input [7:0] in, output out); + +assign out = ~^in; + +endmodule + +// test_simulation_sop_basic_3_test.v +module f5_test(input in, output out); +assign out = ~in; +endmodule + +// test_simulation_sop_basic_7_test.v +module f6_test(input in, output out); +assign out = in; +endmodule + +// test_simulation_sop_basic_8_test.v +module f7_test(output out); +assign out = 1'b0; +endmodule + +// test_simulation_sop_basic_9_test.v +module f8_test(input in, output out); +assign out = ~in; +endmodule |