Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

1 files changed, 7 insertions, 0 deletions

diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v
new file mode 100644
index 000000000..6eec44ade
--- /dev/null
+++ b/tests/errors/syntax_err03.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input [3]x
+);
+endtask
+endmodule
+