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| author | Eddie Hung <eddie@fpgeh.com> | 2020-09-23 09:15:24 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-23 09:15:24 -0700 |
| commit | de79978372c1953e295fa262444cb0a28a246c5f (patch) | |
| tree | 16164e73085755e4d9339b094110ffdbfe588a7e /tests/errors/syntax_err01.v | |
| parent | 81348d2dce84573db39fa081c4549c2e472e49ce (diff) | |
| download | yosys-de79978372c1953e295fa262444cb0a28a246c5f.tar.gz yosys-de79978372c1953e295fa262444cb0a28a246c5f.tar.bz2 yosys-de79978372c1953e295fa262444cb0a28a246c5f.zip | |
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
Diffstat (limited to 'tests/errors/syntax_err01.v')
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