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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 15:51:41 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 15:51:41 +0300 |
| commit | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (patch) | |
| tree | d99a86d4b9f9ba984a39f4760977fdaea29b5b5a /tests/efinix/shifter.v | |
| parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
| download | yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.tar.gz yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.tar.bz2 yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.zip | |
Add new tests for Efinix architecture.
Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
Diffstat (limited to 'tests/efinix/shifter.v')
| -rw-r--r-- | tests/efinix/shifter.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/efinix/shifter.v @@ -0,0 +1,22 @@ +module top (
+out,
+clk,
+in
+);
+ output [7:0] out;
+ input signed clk, in;
+ reg signed [7:0] out = 0;
+
+ always @(posedge clk)
+ begin
+`ifndef BUG
+ out <= out >> 1;
+ out[7] <= in;
+`else
+
+ out <= out << 1;
+ out[7] <= in;
+`endif
+ end
+
+endmodule
|