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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:20:49 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:20:49 +0200 |
| commit | ef417fb1b3555a3075bcd01cb7c5267f3e55b407 (patch) | |
| tree | 80813ffc49a6a645cb28224af9359ebfe12634a5 /tests/efinix/memory.v | |
| parent | 2ed2e9c3e8f2d9d6882588857c8556a6e2af57ea (diff) | |
| parent | eb750670e3835a1bad36cb604e04bf4836cc7f91 (diff) | |
| download | yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.tar.gz yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.tar.bz2 yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.zip | |
Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix
Diffstat (limited to 'tests/efinix/memory.v')
| -rw-r--r-- | tests/efinix/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v new file mode 100644 index 000000000..5634d6507 --- /dev/null +++ b/tests/efinix/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [8:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |