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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 15:51:41 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 15:51:41 +0300 |
commit | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (patch) | |
tree | d99a86d4b9f9ba984a39f4760977fdaea29b5b5a /tests/efinix/latches.v | |
parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
download | yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.tar.gz yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.tar.bz2 yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.zip |
Add new tests for Efinix architecture.
Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
Diffstat (limited to 'tests/efinix/latches.v')
-rw-r--r-- | tests/efinix/latches.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/efinix/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule |