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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 15:51:41 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 15:51:41 +0300 |
commit | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (patch) | |
tree | d99a86d4b9f9ba984a39f4760977fdaea29b5b5a /tests/efinix/adffs.v | |
parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
download | yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.tar.gz yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.tar.bz2 yosys-1070f2e90b9ba37856932189ef09a0f2316d9a21.zip |
Add new tests for Efinix architecture.
Problems/questions:
- fsm.ys. equiv_opt -assert failed because of unproven cells;
- latches.ys,tribuf.ys - internal cells present;
- memory.ys - sat called with -verify and proof did fail.
Diffstat (limited to 'tests/efinix/adffs.v')
-rw-r--r-- | tests/efinix/adffs.v | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v new file mode 100644 index 000000000..05e68caf7 --- /dev/null +++ b/tests/efinix/adffs.v @@ -0,0 +1,87 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffs u_dffs ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnr u_ndffnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule |