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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-03 11:53:37 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-03 11:53:37 +0300 |
commit | 11f330ed223f524cbbdbe2433599990a69b8f380 (patch) | |
tree | 627373ced7ca850efe284caf31c7866cddaa934b /tests/ecp5/memory.v | |
parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
download | yosys-11f330ed223f524cbbdbe2433599990a69b8f380.tar.gz yosys-11f330ed223f524cbbdbe2433599990a69b8f380.tar.bz2 yosys-11f330ed223f524cbbdbe2433599990a69b8f380.zip |
Add tests for ECP5 architecture
Diffstat (limited to 'tests/ecp5/memory.v')
-rw-r--r-- | tests/ecp5/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |