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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:12:18 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:12:18 +0300 |
commit | 134d3fea909bae02f4f814e3d649658502b44b73 (patch) | |
tree | 0a631ddcea2177e98b08779f4b45bf6e2ec39bd8 /tests/ecp5/macc.ys | |
parent | aad9bad32604645e2d61f0858234a1838e8b88eb (diff) | |
download | yosys-134d3fea909bae02f4f814e3d649658502b44b73.tar.gz yosys-134d3fea909bae02f4f814e3d649658502b44b73.tar.bz2 yosys-134d3fea909bae02f4f814e3d649658502b44b73.zip |
Add tests for ecp5 architecture.
Diffstat (limited to 'tests/ecp5/macc.ys')
-rw-r--r-- | tests/ecp5/macc.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..530877727 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:LUT4 +select -assert-count 6 t:CARRY +select -assert-count 7 t:DFFSR +select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D |