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authorSergeyDegtyar <sndegtyar@gmail.com>2019-09-04 12:15:52 +0300
committerSergeyDegtyar <sndegtyar@gmail.com>2019-09-04 12:15:52 +0300
commita203c8569cb6fc7093a5d09e4c64d8e545f81e39 (patch)
tree51c493a25013cb5fc97bce69d435861d8f87ff33 /tests/ecp5/latches.ys
parent55fbc1a355a6139872a176318356ecdb71a35f5d (diff)
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Fix ecp5 tests
- remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;
Diffstat (limited to 'tests/ecp5/latches.ys')
-rw-r--r--tests/ecp5/latches.ys1
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys
index 6eaf77cfd..b9d8faf87 100644
--- a/tests/ecp5/latches.ys
+++ b/tests/ecp5/latches.ys
@@ -14,4 +14,3 @@ cd top
select -assert-count 4 t:LUT4
select -assert-count 1 t:PFUMX
select -assert-none t:LUT4 t:PFUMX %% t:* %D
-write_verilog latches_synth.v