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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-28 09:47:03 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-28 09:47:03 +0300 |
commit | 2270ead09fb4695442c66fe5c06445235f390f2b (patch) | |
tree | 31d55d4e9a9b8af8ca515777af28df492e86f2af /tests/ecp5/latches.v | |
parent | 980830f7b82f2a974f43580f61e917f99fbb4e7e (diff) | |
download | yosys-2270ead09fb4695442c66fe5c06445235f390f2b.tar.gz yosys-2270ead09fb4695442c66fe5c06445235f390f2b.tar.bz2 yosys-2270ead09fb4695442c66fe5c06445235f390f2b.zip |
Add tests for ecp5
Diffstat (limited to 'tests/ecp5/latches.v')
-rw-r--r-- | tests/ecp5/latches.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule |