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author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:28 +0200 |
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committer | GitHub <noreply@github.com> | 2019-10-18 10:54:28 +0200 |
commit | b4d765054897f7ee388b54d907fd8ce607db2d58 (patch) | |
tree | a625838a0efbfb0176a57887c208467a7addd0a6 /tests/ecp5/dpram.v | |
parent | b659082e4a72209af62a19668800bb6334a437d7 (diff) | |
parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
download | yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.gz yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.bz2 yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.zip |
Merge branch 'master' into mmicko/efinix
Diffstat (limited to 'tests/ecp5/dpram.v')
-rw-r--r-- | tests/ecp5/dpram.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1<<addr_width)-1:0] +/* synthesis syn_ramstyle = "no_rw_check" */ ; +always @(posedge wclk) // Write memory. +begin +if (write_en) +mem[waddr] <= din; // Using write address bus. +end +always @(posedge rclk) // Read memory. +begin +dout <= mem[raddr]; // Using read address bus. +end +endmodule |