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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-28 09:47:03 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-28 09:47:03 +0300 |
| commit | 2270ead09fb4695442c66fe5c06445235f390f2b (patch) | |
| tree | 31d55d4e9a9b8af8ca515777af28df492e86f2af /tests/ecp5/add_sub.ys | |
| parent | 980830f7b82f2a974f43580f61e917f99fbb4e7e (diff) | |
| download | yosys-2270ead09fb4695442c66fe5c06445235f390f2b.tar.gz yosys-2270ead09fb4695442c66fe5c06445235f390f2b.tar.bz2 yosys-2270ead09fb4695442c66fe5c06445235f390f2b.zip | |
Add tests for ecp5
Diffstat (limited to 'tests/ecp5/add_sub.ys')
| -rw-r--r-- | tests/ecp5/add_sub.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + |