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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-28 14:45:04 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-28 14:45:04 -0800 |
| commit | 6d143c9a018e5ba352a06785afeba8d50178a835 (patch) | |
| tree | 99a407c011ff773195f889cd04926ec0f5f1a3c1 /tests/asicworld | |
| parent | 64d91219b4e81366976a0e0a9b28efa4bd825022 (diff) | |
| parent | 171c425cf9addb61ef3f03596fd26355ed8af76d (diff) | |
| download | yosys-6d143c9a018e5ba352a06785afeba8d50178a835.tar.gz yosys-6d143c9a018e5ba352a06785afeba8d50178a835.tar.bz2 yosys-6d143c9a018e5ba352a06785afeba8d50178a835.zip | |
Merge pull request #827 from ucb-bar/firrtlfixes
Fix FIRRTL to Verilog process instance subfield assignment.
Diffstat (limited to 'tests/asicworld')
| -rw-r--r-- | tests/asicworld/xfirrtl | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl index c782a2bd6..08bf4ccd8 100644 --- a/tests/asicworld/xfirrtl +++ b/tests/asicworld/xfirrtl @@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v combinational loop code_hdl_models_dff_async_reset.v $adff code_hdl_models_tff_async_reset.v $adff code_hdl_models_uart.v $adff -code_specman_switch_fabric.v subfield assignment (bits() <= ...) code_tidbits_asyn_reset.v $adff code_tidbits_reg_seq_example.v $adff code_verilog_tutorial_always_example.v empty module |