diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
| commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
| tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_verilog_tutorial_which_clock.v | |
| download | yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.gz yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.bz2 yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.zip | |
initial import
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_which_clock.v')
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_which_clock.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_which_clock.v b/tests/asicworld/code_verilog_tutorial_which_clock.v new file mode 100644 index 000000000..418a2cfac --- /dev/null +++ b/tests/asicworld/code_verilog_tutorial_which_clock.v @@ -0,0 +1,12 @@ +module which_clock (x,y,q,d); +input x,y,d; +output q; +reg q; + +always @ (posedge x or posedge y) + if (x) + q <= 1'b0; + else + q <= d; + +endmodule |