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author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_verilog_tutorial_parallel_if.v | |
download | yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.gz yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.bz2 yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.zip |
initial import
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_parallel_if.v')
-rw-r--r-- | tests/asicworld/code_verilog_tutorial_parallel_if.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_parallel_if.v b/tests/asicworld/code_verilog_tutorial_parallel_if.v new file mode 100644 index 000000000..1dbe737eb --- /dev/null +++ b/tests/asicworld/code_verilog_tutorial_parallel_if.v @@ -0,0 +1,21 @@ +module parallel_if(); + +reg [3:0] counter; +wire clk,reset,enable, up_en, down_en; + +always @ (posedge clk) +// If reset is asserted +if (reset == 1'b0) begin + counter <= 4'b0000; +end else begin + // If counter is enable and up count is mode + if (enable == 1'b1 && up_en == 1'b1) begin + counter <= counter + 1'b1; + end + // If counter is enable and down count is mode + if (enable == 1'b1 && down_en == 1'b1) begin + counter <= counter - 1'b1; + end +end + +endmodule |