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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-20 17:13:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-20 17:13:11 +0200 |
| commit | 8e9e793126a2772eed4b041bc60415943c71d5ee (patch) | |
| tree | a899d204b1226f7e4e1fc62d3f66372ae1480ef1 /tests/asicworld/code_verilog_tutorial_fsm_full_tb.v | |
| parent | 1e227caf720bc5870ea9244e6b5657cf9c9717ab (diff) | |
| download | yosys-8e9e793126a2772eed4b041bc60415943c71d5ee.tar.gz yosys-8e9e793126a2772eed4b041bc60415943c71d5ee.tar.bz2 yosys-8e9e793126a2772eed4b041bc60415943c71d5ee.zip | |
Some fixes in tests/asicworld/*_tb.v
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_fsm_full_tb.v')
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_fsm_full_tb.v | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v index 2e9448950..a8e15568b 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v @@ -1,14 +1,14 @@ module testbench(); -reg clock , reset ; +reg clock = 0 , reset ; reg req_0 , req_1 , req_2 , req_3; wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ; +integer file; initial begin // $dumpfile("testbench.vcd"); // $dumpvars(0, testbench); - $display("Time\t R0 R1 R2 R3 G0 G1 G2 G3"); - $monitor("%g\t %b %b %b %b %b %b %b %b", - $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); + file = $fopen(`outfile); + $fdisplay(file, "Time\t R0 R1 R2 R3 G0 G1 G2 G3"); clock = 0; reset = 1; req_0 = 0; @@ -28,6 +28,10 @@ initial begin #10 $finish; end +always @(negedge clock) + $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", + $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); + initial begin #1; forever |