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author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_verilog_tutorial_explicit.v | |
download | yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.gz yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.bz2 yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.zip |
initial import
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_explicit.v')
-rw-r--r-- | tests/asicworld/code_verilog_tutorial_explicit.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_explicit.v b/tests/asicworld/code_verilog_tutorial_explicit.v new file mode 100644 index 000000000..88427ff08 --- /dev/null +++ b/tests/asicworld/code_verilog_tutorial_explicit.v @@ -0,0 +1,35 @@ +module explicit(); +reg clk,d,rst,pre; +wire q; + +// Here q_bar is not connected +// We can connect ports in any order +dff u0 ( +.q (q), +.d (d), +.clk (clk), +.q_bar (), +.rst (rst), +.pre (pre) +); + +endmodule + +// D fli-flop +module dff (q, q_bar, clk, d, rst, pre); +input clk, d, rst, pre; +output q, q_bar; +reg q; + +assign q_bar = ~q; + +always @ (posedge clk) +if (rst == 1'b1) begin + q <= 0; +end else if (pre == 1'b1) begin + q <= 1; +end else begin + q <= d; +end + +endmodule |