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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 14:26:51 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 14:26:51 +0100 |
| commit | 081e1a49f81c298a5c30c4b51241d50ce64f185e (patch) | |
| tree | 8318a8a68cb21d9ea810bdb2554cfcc4e2b0b625 /tests/asicworld/code_verilog_tutorial_comment.v | |
| parent | 9c7f47bbd5fc190578054a6d018760c2f2b62c03 (diff) | |
| download | yosys-081e1a49f81c298a5c30c4b51241d50ce64f185e.tar.gz yosys-081e1a49f81c298a5c30c4b51241d50ce64f185e.tar.bz2 yosys-081e1a49f81c298a5c30c4b51241d50ce64f185e.zip | |
Towards Xilinx bram support
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_comment.v')
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