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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-04-09 09:01:53 -0700 |
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| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2019-04-09 09:01:53 -0700 |
| commit | 5e0339855fc1f83b98694ed37dd2f195c3d8f52c (patch) | |
| tree | 7fdea6df82c102f9f337b3fa23efe0f1860e62ca /tests/asicworld/code_tidbits_reg_seq_example.v | |
| parent | 0deaccbaae436bc94ad5b2913fa39a9368c09ace (diff) | |
| download | yosys-5e0339855fc1f83b98694ed37dd2f195c3d8f52c.tar.gz yosys-5e0339855fc1f83b98694ed37dd2f195c3d8f52c.tar.bz2 yosys-5e0339855fc1f83b98694ed37dd2f195c3d8f52c.zip | |
Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'tests/asicworld/code_tidbits_reg_seq_example.v')
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