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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 14:20:43 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 14:20:43 -0700 |
commit | b97fe6e86651b3a4736c46a49d76878beb088a8c (patch) | |
tree | 14178cb797e6c9a3d7c46ded4d633c11407da9a9 /tests/asicworld/code_hdl_models_parallel_crc.v | |
parent | 9cb0456b6f9fa86240a747bab9780a28001b1a02 (diff) | |
download | yosys-b97fe6e86651b3a4736c46a49d76878beb088a8c.tar.gz yosys-b97fe6e86651b3a4736c46a49d76878beb088a8c.tar.bz2 yosys-b97fe6e86651b3a4736c46a49d76878beb088a8c.zip |
Work in progress for renaming labels/options in synth_xilinx
Diffstat (limited to 'tests/asicworld/code_hdl_models_parallel_crc.v')
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