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author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_hdl_models_mux_using_assign.v | |
download | yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.gz yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.bz2 yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.zip |
initial import
Diffstat (limited to 'tests/asicworld/code_hdl_models_mux_using_assign.v')
-rw-r--r-- | tests/asicworld/code_hdl_models_mux_using_assign.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/asicworld/code_hdl_models_mux_using_assign.v b/tests/asicworld/code_hdl_models_mux_using_assign.v new file mode 100644 index 000000000..4284f10ca --- /dev/null +++ b/tests/asicworld/code_hdl_models_mux_using_assign.v @@ -0,0 +1,22 @@ +//----------------------------------------------------- +// Design Name : mux_using_assign +// File Name : mux_using_assign.v +// Function : 2:1 Mux using Assign +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module mux_using_assign( +din_0 , // Mux first input +din_1 , // Mux Second input +sel , // Select input +mux_out // Mux output +); +//-----------Input Ports--------------- +input din_0, din_1, sel ; +//-----------Output Ports--------------- +output mux_out; +//------------Internal Variables-------- +wire mux_out; +//-------------Code Start----------------- +assign mux_out = (sel) ? din_1 : din_0; + +endmodule //End Of Module mux |