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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 20:44:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:57 -0700 |
| commit | ca4f8c94441c16392ffc02a6117f9b3883e7042e (patch) | |
| tree | b7af1fa8e8c132f47683ad089690e7d92540e951 /tests/asicworld/code_hdl_models_gray_counter.v | |
| parent | 57c478c537ef23c05ca34ecdf4c4334fd82c104e (diff) | |
| download | yosys-ca4f8c94441c16392ffc02a6117f9b3883e7042e.tar.gz yosys-ca4f8c94441c16392ffc02a6117f9b3883e7042e.tar.bz2 yosys-ca4f8c94441c16392ffc02a6117f9b3883e7042e.zip | |
xilinx: gate specify/attributes from iverilog
Diffstat (limited to 'tests/asicworld/code_hdl_models_gray_counter.v')
0 files changed, 0 insertions, 0 deletions