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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 10:28:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-13 10:28:13 -0800 |
| commit | a5764a12365073768edb822e893aa9c0a957e585 (patch) | |
| tree | e4bc3e238923ec29000bbd89252554d5de4a882b /tests/arch | |
| parent | c3262d60752bb20ff5cd54bc4ee6f56e2b772b05 (diff) | |
| download | yosys-a5764a12365073768edb822e893aa9c0a957e585.tar.gz yosys-a5764a12365073768edb822e893aa9c0a957e585.tar.bz2 yosys-a5764a12365073768edb822e893aa9c0a957e585.zip | |
Disable RAM16X1D test
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/lutram.ys | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index a2ede75a5..6c9d1eae1 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -1,20 +1,20 @@ -read_verilog ../common/lutram.v -hierarchy -top lutram_1w1r -chparam A_WIDTH 4 -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd lutram_1w1r -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM16X1D -select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D +#read_verilog ../common/lutram.v +#hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +#proc +#memory -nomap +#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#memory +#opt -full +# +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter +# +#design -load postopt +#cd lutram_1w1r +#select -assert-count 1 t:BUFG +#select -assert-count 8 t:FDRE +#select -assert-count 8 t:RAM16X1D +#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D design -reset |