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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:50:24 +0200 |
commit | 9bd9db56c8ef8ca413f97086fd53609c50df343b (patch) | |
tree | 869984a858e5c9d502ccdfd800618a9c0fe5858a /tests/arch | |
parent | 12383f37b2e1d72784e01db0431efc8882f25430 (diff) | |
download | yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.gz yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.tar.bz2 yosys-9bd9db56c8ef8ca413f97086fd53609c50df343b.zip |
Unify verilog style
Diffstat (limited to 'tests/arch')
-rw-r--r-- | tests/arch/common/add_sub.v | 15 | ||||
-rw-r--r-- | tests/arch/common/adffs.v | 54 | ||||
-rw-r--r-- | tests/arch/common/counter.v | 16 | ||||
-rw-r--r-- | tests/arch/common/dffs.v | 18 | ||||
-rw-r--r-- | tests/arch/common/fsm.v | 98 | ||||
-rw-r--r-- | tests/arch/common/latches.v | 9 | ||||
-rw-r--r-- | tests/arch/common/logic.v | 28 | ||||
-rw-r--r-- | tests/arch/common/mul.v | 12 | ||||
-rw-r--r-- | tests/arch/common/mux.v | 83 | ||||
-rw-r--r-- | tests/arch/common/shifter.v | 9 | ||||
-rw-r--r-- | tests/arch/common/tribuf.v | 6 |
11 files changed, 157 insertions, 191 deletions
diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v index 177c32e30..77e5f5745 100644 --- a/tests/arch/common/add_sub.v +++ b/tests/arch/common/add_sub.v @@ -1,13 +1,12 @@ module top ( - input [3:0] x, - input [3:0] y, + input [3:0] x, + input [3:0] y, - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; + output [3:0] A, + output [3:0] B +); + assign A = x + y; + assign B = x - y; endmodule diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v index 223b52d21..576bd81a6 100644 --- a/tests/arch/common/adffs.v +++ b/tests/arch/common/adffs.v @@ -1,47 +1,43 @@ -module adff - ( input d, clk, clr, output reg q ); +module adff( input d, clk, clr, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; endmodule -module adffn - ( input d, clk, clr, output reg q ); +module adffn( input d, clk, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; endmodule -module dffs - ( input d, clk, pre, clr, output reg q ); +module dffs( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; endmodule -module ndffnr - ( input d, clk, pre, clr, output reg q ); +module ndffnr( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; endmodule diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 52852f8ac..97604d3d8 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -1,17 +1,11 @@ -module top (
-out,
-clk,
-reset
-);
+module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
- if (reset) begin
- out <= 8'b0 ;
- end else
- out <= out + 1;
-
-
+ if (reset)
+ out <= 8'b0;
+ end
+ out <= out + 1;
endmodule
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v index 3418787c9..636252d16 100644 --- a/tests/arch/common/dffs.v +++ b/tests/arch/common/dffs.v @@ -1,15 +1,13 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; +module dff ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; endmodule -module dffe - ( input d, clk, en, output reg q ); +module dffe( input d, clk, en, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk ) - if ( en ) - q <= d; + always @( posedge clk ) + if ( en ) + q <= d; endmodule diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index 368fbaace..9d3fbb64a 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -1,55 +1,51 @@ - module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input clock,reset,req_0,req_1;
- output gnt_0,gnt_1;
- wire clock,reset,req_0,req_1;
- reg gnt_0,gnt_1;
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
- parameter SIZE = 3 ;
- parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+ parameter SIZE = 3;
+ parameter IDLE = 3'b001;
+ parameter GNT0 = 3'b010;
+ parameter GNT1 = 3'b100;
+ parameter GNT2 = 3'b101;
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
- state <= #1 IDLE;
- gnt_0 <= 0;
- gnt_1 <= 0;
- end else
- case(state)
- IDLE : if (req_0 == 1'b1) begin
- state <= #1 GNT0;
- gnt_0 <= 1;
- end else if (req_1 == 1'b1) begin
- gnt_1 <= 1;
- state <= #1 GNT0;
- end else begin
- state <= #1 IDLE;
- end
- GNT0 : if (req_0 == 1'b1) begin
- state <= #1 GNT0;
- end else begin
- gnt_0 <= 0;
- state <= #1 IDLE;
- end
- GNT1 : if (req_1 == 1'b1) begin
- state <= #1 GNT2;
- gnt_1 <= req_0;
- end
- GNT2 : if (req_0 == 1'b1) begin
- state <= #1 GNT1;
- gnt_1 <= req_1;
- end
- default : state <= #1 IDLE;
- endcase
- end
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end
+ else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
endmodule
diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v index adb5d5319..60b757103 100644 --- a/tests/arch/common/latches.v +++ b/tests/arch/common/latches.v @@ -1,19 +1,16 @@ -module latchp - ( input d, clk, en, output reg q ); +module latchp ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule -module latchn - ( input d, clk, en, output reg q ); +module latchn ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule -module latchsr - ( input d, clk, en, clr, pre, output reg q ); +module latchsr ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v index e5343cae0..c17899fa0 100644 --- a/tests/arch/common/logic.v +++ b/tests/arch/common/logic.v @@ -1,18 +1,16 @@ module top ( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 +); + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; endmodule diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index d5b48b1d7..437a91cfc 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,11 +1,9 @@ module top ( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; + input [5:0] x, + input [5:0] y, + output [11:0] A, +); + assign A = x * y; endmodule diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v index 27bc0bf0b..71c1ac7f2 100644 --- a/tests/arch/common/mux.v +++ b/tests/arch/common/mux.v @@ -8,51 +8,47 @@ module mux2 (S,A,B,Y); endmodule module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - + input[1:0] S; + input[3:0] D; + output Y; + + reg Y; + wire[1:0] S; + wire[3:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase + end endmodule module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - + input[2:0] S; + input[7:0] D; + output Y; + + reg Y; + wire[2:0] S; + wire[7:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase + end endmodule module mux16 (D, S, Y); @@ -60,6 +56,5 @@ module mux16 (D, S, Y); input [3:0] S; output Y; -assign Y = D[S]; - + assign Y = D[S]; endmodule diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index 04ae49d83..cace3b588 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,8 +1,4 @@ -module top (
-out,
-clk,
-in
-);
+module top(out, clk, in);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
@@ -11,6 +7,5 @@ in begin
out <= out >> 1;
out[7] <= in;
- end
-
+ end
endmodule
diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v index c64468253..e1d701611 100644 --- a/tests/arch/common/tribuf.v +++ b/tests/arch/common/tribuf.v @@ -1,8 +1,8 @@ -module tristate (en, i, o); +module tristate(en, i, o); input en; input i; output reg o; - + always @(en or i) - o <= (en)? i : 1'bZ; + o <= (en)? i : 1'bZ; endmodule |