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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 15:18:01 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-28 15:18:01 +0100 |
| commit | 903f9973913371452005eb173ac50fec1d5d1447 (patch) | |
| tree | b160b35c7a1048dc5d1ef2f63a6159f5aef6fe1f /tests/arch | |
| parent | 9517525224c7bc4b8ac7d093066485888a337b76 (diff) | |
| download | yosys-903f9973913371452005eb173ac50fec1d5d1447.tar.gz yosys-903f9973913371452005eb173ac50fec1d5d1447.tar.bz2 yosys-903f9973913371452005eb173ac50fec1d5d1447.zip | |
add tristate buffer and test
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/gowin/tribuf.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys new file mode 100644 index 000000000..5855b9d97 --- /dev/null +++ b/tests/arch/gowin/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:TBUF +select -assert-count 2 t:IBUF +select -assert-none t:TBUF t:IBUF %% t:* %D |