diff options
| author | Diego H <diego@symbioticeda.com> | 2019-12-16 10:23:45 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-16 10:23:45 -0600 |
| commit | 87e21b0122bd682db8aeffae3e1ac503c9cea2d2 (patch) | |
| tree | 78f11723d9aa575fd7a278af75719b29d22215d0 /tests/arch | |
| parent | f3f59910eb06bf74a2a4b8157797a327dd097451 (diff) | |
| download | yosys-87e21b0122bd682db8aeffae3e1ac503c9cea2d2.tar.gz yosys-87e21b0122bd682db8aeffae3e1ac503c9cea2d2.tar.bz2 yosys-87e21b0122bd682db8aeffae3e1ac503c9cea2d2.zip | |
Fixing compiler warning/issues. Moving test script to the correct place
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/attributes_test.ys (renamed from tests/arch/common/memory_attributes/attributes_test.ys) | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys index 4e06a35e7..4c881b280 100644 --- a/tests/arch/common/memory_attributes/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -1,5 +1,5 @@ # Check that blockram memory without parameters is not modified -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram synth_xilinx -top block_ram cd block_ram # Constrain all select calls below inside the top module @@ -7,7 +7,7 @@ select -assert-count 1 t:RAMB18E1 # Check that distributed memory without parameters is not modified design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram synth_xilinx -top distributed_ram cd distributed_ram # Constrain all select calls below inside the top module @@ -15,7 +15,7 @@ select -assert-count 8 t:RAM32X1D # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set ram_style "distributed" block_ram synth_xilinx -top block_ram @@ -24,7 +24,7 @@ select -assert-count 32 t:RAM128X1D # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set logic_block 1 block_ram synth_xilinx -top block_ram @@ -34,14 +34,14 @@ select -assert-count 32 t:RAM128X1D # Set ram_style block to a distributed memory; will be implemented as blockram design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v synth_xilinx -top distributed_ram_manual cd distributed_ram_manual # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 # Set synthesis, ram_block block to a distributed memory; will be implemented as blockram design -reset -read_verilog attributes_test.v +read_verilog ../common/memory_attributes/attributes_test.v synth_xilinx -top distributed_ram_manual_syn cd distributed_ram_manual_syn # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 |