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authorEddie Hung <eddie@fpgeh.com>2019-12-12 17:49:55 -0800
committerEddie Hung <eddie@fpgeh.com>2019-12-12 17:49:55 -0800
commit037d1a03df20b9c445790728bb80e1818d1edafa (patch)
tree9cb4e67449b5f1f8589a886abc17035572dca27e /tests/arch
parent7a9d1be97d100c265530270810071e2e9e676b3e (diff)
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Add #1460 testcase
Diffstat (limited to 'tests/arch')
-rw-r--r--tests/arch/xilinx/bug1460.ys34
1 files changed, 34 insertions, 0 deletions
diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys
new file mode 100644
index 000000000..2018071cc
--- /dev/null
+++ b/tests/arch/xilinx/bug1460.ys
@@ -0,0 +1,34 @@
+read_verilog <<EOT
+module register_file(
+ input wire clk,
+ input wire write_enable,
+ input wire [63:0] write_data,
+ input wire [4:0] write_reg,
+ input wire [4:0] read1_reg,
+ input wire [4:0] read2_reg,
+ input wire [4:0] read3_reg,
+ output reg [63:0] read1_data,
+ output reg [63:0] read2_data,
+ output reg [63:0] read3_data
+ );
+
+ reg [63:0] registers[0:31];
+
+ always @(posedge clk) begin
+ if (write_enable == 1'b1) begin
+ registers[write_reg] <= write_data;
+ end
+ end
+
+ always @(all) begin
+ read1_data <= registers[read1_reg];
+ read2_data <= registers[read2_reg];
+ read3_data <= registers[read3_reg];
+ end
+endmodule
+EOT
+
+synth_xilinx
+cd register_file
+select -assert-count 32 t:RAM32M
+select -assert-none t:* t:BUFG %d t:RAM32M %d